1. Field of the Invention
The present invention relates to a data read system for a semiconductor storage device having a memory cell, and more specifically to a semiconductor storage device and data reading method capable of reducing a circuit area of a sense amplifier used in reading data, and increasing an access speed.
2. Description of the Related Art
Recently, a ferroelectric memory read system called a bit line GND sense system has been proposed. (Refer to Japanese Published Patent Application No. 2002-133857 (“Data Read Circuit, Data Reading Method, and Data Storage Device”)), Japanese Published Patent Application No. 2005-293818 (“Semiconductor Memory”), and “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM” (S. Kawashima, T. Endo, A. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, and M. Aoki, IEEE Jour. Solid-State Circuits, Vol. 37, No. 5, pp. 592-598, May 2002).) In this read system, the charge flowing from a memory cell to a bit line is transferred to a charge accumulation circuit through a charge transfer circuit called a charge transfer in a presense amplifier so that the voltage of a bit line cannot fluctuate when a voltage is applied to a plate line for a memory cell, and a logical value of the data held in the memory cell can be judged depending on the amount of charge transferred to the charge accumulation circuit.
The charge transfer is normally constituted by a pMOS transistor, and the gate-to-source voltage of the pMOS transistor is initialized to the same value as the threshold voltage before a voltage is applied to a plate line. The gate voltage of the pMOS transistor is controlled by an inverter amplifier in which output voltage drops as the voltage of a bit line rises.
FIG. 1 shows the circuit configuration of a conventional technique of a presense amplifier for reading data in a memory cell. A conventional technique of reading data from a memory cell using the bit line GND sense system is explained by referring to FIG. 1.
In FIG. 1, a presense amplifier 100 comprises: an nMOS transistor 102 for use in initializing bit line potential, in which a bit line BL (BLE or BLO) from a memory cell 101 is connected to the drain, the source is connected to the ground line, and a control signal BGND is applied to the gate; a pMOS transistor 103 for functioning as a charge transfer that transfers the charge flowing through the bit line when data is read from the memory cell 101 as described above, in which the source is connected to the bit line BL, the drain is connected to a negative voltage generation circuit described later and a level shift circuit (node MINUS), and the output node VTH of the threshold voltage generation circuit described later is connected to the gate; an inverter amplifier 104 connected between the bit line BL and the gate of the pMOS transistor 103 used as a charge transfer; a threshold voltage generation circuit 105 operating as a circuit for initializing the gate voltage of the pMOS transistor 103 as a charge transfer; a negative voltage generation circuit 106 for generating a negative voltage to allow the pMOS transistor 103 to implement the operation as a charge transfer; and a level shift circuit 107 for converting a negative voltage generated by the negative voltage generation circuit 106 into a positive voltage are provided. The output of the level shift circuit 107 is applied to the sense amplifier as described later.
The inverter amplifier 104 comprises: a CMOS inverter 110 (feedback inverter); a switch 112 for connecting an output terminal IOUT of the CMOS inverter 110 to an input terminal IIN; a capacitor 113 disposed between the input terminal IIN of the CMOS inverter 110 and the bit line BL; and a capacitor 114 disposed between the output terminal IOUT of the CMOS inverter 110 and the gate of the transistor 103 for charge transfer. The source of the pMOS transistor (not shown in the attached drawings) of the CMOS inverter 110 is connected to the power line VDD through a pMOS transistor 115 receiving a power control signal POWX at the gate. The source of the nMOS transistor (not shown in the attached drawings) of the CMOS inverter 110 is connected to the ground line through an nMOS transistor 116 receiving a power control signal POW at the gate. The power control signals POWX and POW are respectively changed to a low level and a high level when a reading operation is started, thereby activating the CMOS inverter 110. Similarly, the switch 112 is turned off when the reading operation is started. The capacitors 113 and 114 are constituted by, for example, a ferroelectric capacitor.
The threshold voltage generation circuit 105 has two transistors 117 and 118 constituting a voltage generation circuit for applying a high level (power voltage VDD) or low level (ground voltage) to a node VGENX, a capacitor 119 connected between the node VGENX and the node VTH, two transistors 121 and 122 constituting a clamping circuit connected to the node VTH, and a switch for connecting a clamping circuit to a ground line.
The voltage generation circuit has the pMOS transistor 117 and the nMOS transistor 118 connected in series between a power line VDD and a ground line. The gates of the pMOS transistor 117 and the nMOS transistor 118 respectively receive a voltage control signals VGENP and VGENN. The clamping circuit is constituted by the pMOS transistor 121, in which the source is connected to the ground line through the switch 123, and the gate and drain are connected to the node VTH, and the nMOS transistor 122, in which the gate and source are connected to the ground line, and the drain is connected to the node VTH. The capacitor 119 is constituted by, for example, a ferroelectric capacitor.
The negative voltage generation circuit 106 has a CMOS inverter 125 which receives a negative voltage control signal MGEN, and the output is connected to a node MGENX and a capacitor 126 disposed between the node MGENX and the node MINUS. The capacitor 126 is constituted by, for example, a ferroelectric capacitor.
The level shift circuit 107 has a capacitor (not shown in the attached drawings) for converting a negative voltage generated in the node MINUS into a positive voltage, an nMOS transistor, and a pMOS transistor.
FIG. 2 shows a reading operation from ferroelectric memory according to the conventional technology shown in FIG. 1. First, in the initial state, the node MINUS connected to the drain of the pMOS transistor 103 (for charge transfer) is in a floating state. Therefore, the voltage is unstable. However, since the source and the drain (p-type diffusion layer) of the pMOS transistor 103, and the back gate (n-type diffusion layer, ground voltage) form a pn junction, the voltage of the node MINUS does not rise over the voltage (about 0.8 V) in the pn junction forward direction. On the other hand, since the node VTH connected to the gate of the pMOS transistor 103 (for charge transfer) is likewise in the floating state, the potential is unstable. However, by the pMOS transistor 122 disposed in the clamping circuit, the potential of the node VTH does not rise over the threshold voltage (about 0.6 V) of the pMOS transistor.
The voltage control signals VGENP and VGENN, and the negative voltage control signal MGEN are held at a low level, and the nodes VGENX and MGENX are held at a high level. Since the control signal BGND is held at a high level, the nMOS transistor 102 (for initializing a bit line) is turned on, and the voltage of the bit line BL (BLE or BLO) is initialized to the ground voltage. The power control signals POW and POWX are respectively held in the high level and the low level, and the feedback inverter 110 (CMOS inverter) is turned off. The switches 112 and 113 are turned on.
At time T1, the power control signals POW and POWX are respectively changed into the high level and the low level, and the feedback inverter 110 is activated. Since the switch 112 is turned on, the input voltage IIN and the output voltage IOUT of the feedback inverter 110 are substantially VDD/2.
At time T2, the voltage control signals VGENP and VGENN are changed into the high level, and the node VGENX is changed from the high level to the low level. By the capacity coupling by the capacitor 119, the voltage of the node VTH drops depending on the change of the node VGENX to the low level. When the power voltage VDD is 3V and the voltage of the node VGENX drops by 3V, the voltage of the VTH is to also drop by 3V. However, by turning on the switch 123, the pMOS transistor 121 (clamping circuit) clamps the voltage of the node VTH to the threshold voltage (for example, −0.6 V) of the pMOS transistor 121. Therefore, the voltage of the node VTH once falls, and then indicates a differentiation waveform and is fixed to a negative voltage (−0.6 V). Thus, the threshold voltage generation circuit 105 operates as an initialization circuit for setting the node VTH to a predetermined voltage.
The threshold voltage of the pMOS transistor 103 is designed to be equal to the threshold voltage of the pMOS transistor 121. Therefore, when the voltage of the node VTH once falls, the pMOS transistor 103 is turned on, and the voltage of the node MINUS drops to the voltage (ground voltage) of the bit line BL.
On the other hand, since the voltage of the node MGENX is set to the high level (=power voltage VDD) by the CMOS inverter 125, the capacitor 126 is charged with the charge corresponding to the product of the capacity value and the power voltage VDD.
At time T3, the voltage control signal VGENN changes into a low level, and the nMOS transistor 118 of the voltage generation circuit is turned off. Since the pMOS transistor 117 of the voltage generation circuit has already been turned off, the node VGENX becomes the floating state. Simultaneously, the switches 112 and 123 are turned off. By turning off the switch 123, the clamp of the node VTH by the pMOS transistor 121 is released. By turning off the switch 112, the short between the input and the output of the feedback inverter 110 is released. Since the input voltage of the feedback inverter 110 is VDD/2 substantially, the feedback inverter 110 operates as an inverter amplifier having a high gain. On the other hand, the control signal BGND is also changed to a low level, and the bit line BL becomes a floating state. Thus, after time T3, when the voltage of the bit line BL rises, the capacity coupling of the capacitor 113 raises the input voltage IIN of the feedback inverter 110. The feedback inverter 110 amplifies the change of the input voltage IIN, and drops the output voltage IOUT in the opposite direction. The capacity coupling of the capacitor 114 drops the voltage of the node VTH according to the change of the output voltage IOUT.
At time T4, the negative voltage control signal MGEN changes to a high level, and the voltage of the node MGENX changes from a high level to a low level. The voltage of the node MINUS drops with the fall of the voltage of the node MGENX by the capacity coupling of the capacitor 126. When the power voltage VDD is 3V, the voltage of the node MGENX drops by 3V. Since the voltage of the node MINUS is initialized to 0V, it drops to substantially −3V by the voltage change of the node MGENX. However, the voltage of the node MINUS is higher than −3V by the loss from a parasitic capacity and the leakage current of the pMOS transistor 103 which has already been turned on.
The voltage of the node MINUS is held at the above-mentioned voltage by the capacitor 126. Thus, the negative voltage generation circuit 106 operates as an initialization circuit for setting the voltage of the node MINUS in the initial state, and setting the charge transfer capability of the pMOS transistor 103 in the initial state.
At time T5, the voltage of the word line WL and the plate line PL changes from the ground voltage to the power voltage VDD. By the rise of the word line WL, the access transistor N1 of the memory cell MC 101 is turned on, and a positive voltage is applied to the ferroelectric capacitor F1 of the memory cell MC. When the memory cell MC 101 stores the data “1”, the polarity of the voltage applied to the ferroelectric capacitor F1 is the inverse of the writing operation, thereby causing a polarization inversion, and reading large inverse charge to the bit line BL. When the memory cell 101 stores data “0”, the polarity of the voltage applied to the ferroelectric capacitor F1 is the same as in the writing operation, and no polarization inversion occurs and a relatively small charge is read to the bit line BL. At this time, the voltage of the bit line BL tends to rise.
However, when the voltage of the bit line BL rises a little bit, the input voltage IIN of the feedback inverter 110 rises by the capacity coupling of the capacitor 113. By the inversion and amplification effects of the feedback inverter 110 and the capacity coupling of the capacitor 114, the voltage of the node VTH drops, and the gate-to-source voltage (absolute value) of the pMOS transistor 103 becomes large. Therefore, a drain current occurs in the pMOS transistor 103, and the charge read to the bit line BL is transferred from the bit line BL to the node MINUS. As a result, the rise of the charge of the bit line BL is suppressed, and is maintained at substantially 0 V (ground voltage). Thus, the feedback inverter 110 operates as a control circuit for adjusting the charge transfer capability of the charge transfer transistor 103. Since the capacitor 126 is discharged by the charge transferred to the node MINUS, the voltage (read voltage) of the node MINUS rises. Thus, the capacitor 126 of the negative voltage generation circuit 106 operates as a read circuit for generating a read voltage depending on the accumulated charge.
In the conventional technology of the bit line GND sense system explained by referring to FIGS. 1 and 2, when the voltage of the bit line rises in the operation of reading data from a memory cell, the operation of opening a gate of the pMOS transistor for a charge transfer and transferring the charge to the sense amplifier is performed. The difference between when “1” is read as data from a memory cell, that is, the potential rise of the bit line in the term P, and when “0” is read as data, that is, the potential rise of the bit line in the term U, is amplified by a sense amplifier, and the logical value of the data is judged.
However, with a finer semiconductor integrated circuit and smaller memory cell to realize large-capacity memory, it is necessary to reduce the area of a sense amplifier. In the conventional bit line GND sense system, a circuit for generating a negative voltage is required to transfer charge to a charge accumulation circuit, and there is the problem that the circuit is a bottleneck in reducing the size of a circuit. Furthermore, the time to initialize the negative voltage generation circuit is also required, and it is a bottleneck in realizing high-speed access.